1. Field of the Invention
The present invention relates to nonvolatile dynamic semiconductor memories and, more particularly, to an electrically erasable programmable read-only memory.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, there has been strongly demanded a semiconductor memory having a large data storage capacity for replacing an existing external data storage device such as a magnetic floppy disk drive unit, a fixed disk unit, etc. Although presently available electrically erasable programmable read-only memories have a technical merit such that a high-speed data write/read operation can be realized with high reliability, these memories have not been improved to obtain a sufficient data storage capacity.
One reason for the above problem is as follows. That is, in a conventional electrically erasable programmable read-only memory (to be referred to as an "EEPROM" hereinafter), each memory cell for storing 1-byte data is basically constituted by two transistors. With such an arrangement, only when a specific high-integration element fabrication technique is employed, a cell area on a chip substrate cannot simply be decreased. According to the existing semiconductor fabrication technology, a satisfactory specific element fabrication technique for this purpose is not established. Even if such a specific element fabrication technique is established, low productivity prevents practical applications of the technique.
In order to solve the above problem, recently, a specific type of EEPROM having a "NAND cell" structure has been proposed wherein each memory cell is constituted by only one transistor (field effect transistor), and a number of memory cells are connected in series in each array, whereby the number of contact portions between the cell array and the corresponding bit line is remarkably decreased, so that the integration density can be greatly improved.
The presently proposed "NAND cell" type EEPROM, however, suffers from insufficient efficiency of a data write operation. More specifically, according to the existing NAND cell type EEPROM, a state wherein electrons are tunnel-injected into a floating gate of each memory cell so that a threshold value of each memory cell transistor is shifted in the positive direction is defined as an "erase state". When a certain memory cell is selected and logical data is written therein, the NAND array to which the certain memory cell belongs is electrically connected to a corresponding bit line. When the potential of write data is transferred from the corresponding bit line to the selected memory cell through non-selected memory cell transistors in the NAND cell array, a voltage drop necessarily occurs in each of these non-selected memory cell transistors. The voltage drop causes a decrease in effective potential of the write data supplied from the bit line, thus degrading the efficiency of a write operation.
In particular, when the integration density of the EEPROM is increased and the number of memory cells arranged in each NAND cell array is increased along with the increase in integration density, the above-mentioned voltage drop is further increased. Therefore, it may be easily imagined that a problem of a decrease in write efficiency in the EEPROM becomes more serious.
Even if the integration density of the EEPROM remains the same, when a large number of write and erase operations of data are repeated, in the NAND cell array, the threshold values of the non-selected memory cells located between the corresponding bit line associated therewith and the selected memory cell tend to be gradually increased upon each data erase operation. Since this gradual increase in threshold values prevents effective transfer of the write data in the selected memory cell in the NAND cell array, the write efficiency is degraded, as a matter of course. In addition, if the threshold values of these non-selected memory cells are simply increased to exceed a predetermined read voltage in the EEPROM, a reliable data read operation cannot be performed, and the probability of generation of read error is undesirably increased.